1. Field of the Invention
The present disclosure relates to a thin film transistor (or “TFT”) substrate having a metal oxide semiconductor for the fringe field type flat panel displays and a method for manufacturing the same. Especially, the present disclosure relates to a thin film transistor substrate for the flat panel display in which an oxide semiconductor material is used for an active layer, a source-drain electrode and a pixel electrode by simplifying the manufacturing mask process, and a manufacturing method the same.
2. Discussion of the Related Art
Nowadays, as the information society is developed, the requirements of displays for representing information are increasing. Accordingly, the various flat panel displays (or ‘FPD’) are developed for overcoming many drawbacks of the cathode ray tube (or ‘CRT’) such as heavy weight and bulk volume. The flat panel display devices include the liquid crystal display device (or ‘LCD’), the field emission display (or ‘FED’), the plasma display panel (or ‘PDP’), the organic light emitting display device (or ‘OLED’) and the electrophoresis display device (or ‘ED’).
The display panel of a flat panel display may include a thin film transistor substrate having a thin film transistor allocated in each pixel region arrayed in a matrix manner. For example, the liquid crystal display device represents video data by controlling the light transitivity of the liquid crystal layer using the electric fields. According to the direction of the electric field, the LCD can be classified in the two major types; one is vertical electric field type and the other is the horizontal electric field type.
For the vertical electric field type LCD, a common electrode formed on an upper substrate and a pixel electrode formed on a lower substrate are facing with each other for forming an electric field of which direction is perpendicular to the substrate face. A twisted nematic (TN) liquid crystal layer disposed between the upper substrate and the lower substrate is driven by the vertical electric field. The vertical electric field type LCD has merit of higher aperture ratio, while it has demerit of narrower view angle about 90 degree.
For the horizontal electric field type LCD, a common electrode and a pixel electrode are formed on the same substrate in parallel. A liquid crystal layer disposed between an upper substrate and a lower substrate is driven in In-Plane-Switching (or ‘IPS’) mode by an electric field parallel to the substrate face. The horizontal electric field type LCD has a merit of wider view angle over 160 degrees and faster response speed than the vertical electric field type LCD. However, the horizontal electric field type LCD may have demerits such as low aperture ratio and transitivity ratio of the back light.
In the IPS mode LCD, for example, in order to form the in-plane electric field, the gap between the common electrode and the pixel electrode may be larger than the gap (or “Cell Gap”) between the upper substrate and the lower substrate, and in order to get enough strength of the electric field, the common electrode and the pixel electrode may have a strip pattern having certain width. Between the pixel electrode and the common electrode of the IPS mode LCD, the electric field horizontal with the substrate is formed. However, just over the pixel electrode and the common electrode, there is no electric field. That is, the liquid crystal molecules disposed just over the pixel electrodes and the common electrodes are not driven but maintain the initial conditions (the initial alignment direction). As the liquid crystal molecules in the initial condition cannot control the light transitivity properly, the aperture ratio and the luminescence may be degraded.
For resolving these demerits of the IPS mode LCD, the fringe field switching (or ‘FFS’) type LCD driven by the fringe electric field has been proposed. The FFS type LCD comprises the common electrode and the pixel electrode with the insulating layer there-between, and the gap between the pixel electrode and the common electrode is set narrower than the gap between the upper substrate and the lower substrate. So that, a fringe electric field having a parabola shape is formed in the space between the common electrode and the pixel electrode as well over these electrodes. Therefore, most of all liquid crystal molecules disposed between the upper substrate and the lower substrate can be driven by this fringe field. As a result, it is possible to enhance the aperture ratio and the front luminescence.
For the fringe field type liquid crystal display, the common electrode and the pixel electrode are disposed closely each other or in an overlapped manner, so that a storage is formed between the common electrode and the pixel electrode. Therefore, the fringe field type liquid crystal display has a merit in that there is no extra space for forming the storage in the pixel region. However, when a large area display is formed in a fringe field type, the pixel region would be getting larger and the storage would be getting larger and larger. In that case, the thin film transistor should have also larger size for driving/charging the enlarged storage in a short time period.
To solve this problem, the thin film transistor having a metal oxide semiconductor material is applied because it has the high current control characteristics without enlarging the size of the thin film transistor. FIG. 1 is a plane view illustrating a thin film transistor substrate having an oxide semiconductor layer included in a fringe field type liquid crystal display according to the related art. FIG. 2 is a cross-sectional view illustrating the structure of the thin film transistor substrate of FIG. 1 by cutting along the line I-I′ according to the related art.
The thin film transistor substrate having a metal oxide semiconductor layer shown in FIGS. 1 and 2 comprises a gate line GL and a data line DL crossing each other with a gate insulating layer GI therebetween on a lower substrate SUB, and a thin film transistor T formed at each crossing portion. By the crossing structure of the gate line GL and the data line DL, a pixel region is defined.
The thin film transistor T comprises a gate electrode G branched (or ‘extruded’) from the gate line GL, a source electrode S branched from the data line DL, a drain electrode D facing the source electrode S and connecting to the pixel electrode PXL, and a semiconductor layer A overlapping with the gate electrode G on the gate insulating layer GI for forming a channel between the source electrode S and the drain electrode D.
The semiconductor layer A made of the oxide semiconductor material has a merit for a large area thin film transistor substrate having a large charging capacitance, thanks to the high electron mobility of the oxide semiconductor layer. However, the thin film transistor having the oxide semiconductor material would have an etch stopper ES for protecting the upper surface of the semiconductor layer from the etching material for ensuring the stability and the characteristics of the thin film transistor. More detail, it is proper to have an etch stopper ES for protecting the semiconductor layer A from the etchant used for forming the source electrode S and the drain electrode D there-between.
At one end of the gate line GL, a gate pad GP is formed for receiving the gate signal. The gate pad GP is connected to a gate pad intermediate terminal IGT through the first gate pad contact hole GH1 penetrating the gate insulating layer GI. The gate pad intermediate terminal IGT is connected to the gate pad terminal GPT through the second gate pad contact hole GH2 penetrating the first passivation layer PA1 and the second passivation layer PA2. Further, at one end of the data line DL, a data pad DP is formed for receiving the pixel signal. The data pad DP is connected to a data pad terminal DPT through the data pad contact hole DPH penetrating the first passivation layer PA1 and the second passivation layer PA2.
In the pixel region, a pixel electrode PXL and a common electrode COM are formed with the second passivation layer PA2 there-between, to form a fringe electric field. The common electrode COM is connected to the common line CL disposed in parallel with the gate line GL. The common electrode COM is supplied with a reference voltage (or “common voltage”) via the common line CL.
The common electrode COM and the pixel electrode PXL can have various shapes and positions according to the design purpose and environment. While the common electrode COM is supplied with a reference voltage having constant value, the pixel electrode PXL is supplied with a data voltage varying timely according to the video data. Therefore, between the data line DL and the pixel electrode PXL, a parasitic capacitance may be formed. Due to the parasitic capacitance, the video quality of the display may be degraded. Therefore, it is preferable to form the common electrode COM at first and then the pixel electrode PXL is formed at the topmost layer.
In other words, on the first passivation layer PA1 covering the data line DL and the thin film transistor T, a planarization layer PAC formed by thickly depositing an organic material having a low permittivity. Then, the common electrode COM is formed. And then, after depositing the second passivation layer PA2 to cover the common electrode COM, the pixel electrode PXL overlapping with the common electrode is formed on the second passivation layer PA2. In this structure, the pixel electrode PXL is far from the data line DL by the first passivation layer PA1, the planarization layer PAC and the second passivation layer PA2, so that it is possible to reduce the parasitic capacitance between the data line DL and the pixel electrode PXL.
The common electrode COM is formed to a rectangular shape corresponding to the pixel region. The pixel electrode PXL is formed to have a plurality of segments. Especially, the pixel electrode PXL is vertically overlapped with the common electrode COM with the second passivation layer PA2 there-between. Between the pixel electrode PXL and the common electrode COM, the fringe electric field is formed. By this fringe electric field, the liquid crystal molecules arrayed in plane direction between the thin film transistor substrate and the color filter substrate may be rotated according to the dielectric anisotropy of the liquid crystal molecules. According to the rotation degree of the liquid crystal molecules, the light transmittance ratio of the pixel region may be changed so as to represent desired gray scale.
Hereinafter, we will explain about the method for manufacturing a FFS type thin film transistor substrate having the oxide semiconductor according to the related art. FIGS. 3A to 31 are cross-sectional views along to the cutting line I-I′ in FIG. 1 for illustrating the manufacturing processes of the fringe field type thin film transistor according to the related art.
As shown in FIG. 3A, on a transparent lower substrate SUB, a gate metal is deposited. Patterning the gate metal using the first mask process, the gate elements are formed. The gate elements include a gate line GL, a gate electrode G branched out from the gate line GL, and a gate pad GP formed at one end of the gate line GL.
As shown in FIG. 3B, on the whole surface of the substrate SUB having the gate elements, a gate insulating layer GI is deposited. And then, an oxide semiconductor material is sequentially deposited. Patterning the oxide semiconductor material using the second mask process, a semiconductor layer A is formed.
As shown in FIG. 3C, on the whole surface of the substrate SUB having the semiconductor layer A, an insulating material such as a silicon nitride (SiNx) or a silicon oxide (SiOx) is deposited. Patterning the insulating material using the third mask process, an etch stopper ES is formed. It is preferable that the etch stopper ES is positioned on the middle portion of the semiconductor layer A overlapped with the gate electrode G.
As shown in FIG. 3D, using the fourth mask process, the gate insulating layer GI deposited at the topmost layer of the substrate SUB having the etch stopper ES is patterned to form the first gate pad contact hole GH1 exposing all or some portions of the gate pad GP.
On the substrate SUB having the semiconductor A and the etch stopper ES, a source-drain metal is deposited. Patterning the source-drain metal using the fifth mask process, the source-drain elements are formed. The source-drain elements include a data line DL crossing with the gate line GL, a gate pad intermediate terminal IGT connecting to the gate pad GP through the first gate pad contact hole GH1, a data pad DP formed at one end of the data line DL, a source electrode S branching out from the data line and connecting to one side of the semiconductor layer A, and a drain electrode D facing to the source electrode S with a predetermined distance and connecting to the other side of the semiconductor layer A. Especially, the source electrode S and the drain electrode D are physically disconnected each other, but they are linked through the semiconductor layer A.
In the case that etch stopper ES is not included, during patterning the source electrode S and the drain electrode D, the middle portions of the semiconductor layer A between the source electrode S and the drain electrode D may be etched by the etchant, so called ‘Back Etch’. When the semiconductor layer A is made of the amorphous semiconductor, the Back Etch may not cause a big problem to the element characteristics. However, when the semiconductor layer A is made of the oxide semiconductor material, the Back Etch may cause a severe problem to the element characteristics and/or stability. Therefore, when the channel layer of the thin film transistor includes the oxide semiconductor material, it is preferable that the etch stopper ES is formed to protect the channel layer, as shown in FIG. 3E.
As shown in FIG. 3F, on the whole surface of the substrate SUB having the thin film transistor T, the first passivation layer PA1 is deposited. Then, using an organic material having a lower permittivity, a planarization layer PAC is deposited. Patterning the planarization layer PAC using the sixth mask process, the first drain contact hole DH1 is formed. The first drain contact hole DH1 does not expose the drain electrode D at all in this stage. The second passivation layer PA2 which will be formed later has the second drain contact hole DH2 exposing the drain electrode D. As the planarization layer PAC is relatively thick than any other layers, in order to make easy to form the second drain contact hole DH2 and to ensure the enough contact area of the exposed portions of the drain electrode D, the first drain contact hole DH1 is formed in advance. Further, on the gate pad GP and the data pad DP, removing some portions of the planarization layer PAC, some portions of the first passivation layer PA1 are exposed.
As shown in FIG. 3G, on the whole surface of the substrate SUB having the planarization layer PAC, a transparent conductive material such as an indium tin oxide (or ‘ITO’). Patterning the transparent conductive layer using the seventh mask process, a common electrode COM is formed. The common electrode COM may have a rectangular shape corresponding to the shape and area of the pixel region.
As shown in FIG. 3H, on the whole surface of the substrate SUB having the common electrode COM, the second passivation layer PA2 is deposited. Patterning the first and the second passivation layers PA1 and PA2 using the eighth mask process, the second gate pad contact hole GH2 exposing the gate pad intermediate terminal IGT, the data pad contact hole DPH exposing some portions of the data pad DP, and the second drain contact hole DH2 exposing the drain electrode D are formed.
As shown in FIG. 3I, on the second passivation layer PA2, another transparent conductive material such as ITO is deposited. Patterning the transparent conductive material using the ninth mask process, a pixel electrode PXL, a gate pad terminal GPT and the data pad terminal DPT are formed. The pixel electrode PXL is overlapped with the common electrode COM on the second passivation layer PA2. Especially, the pixel electrode PXL has a plurality of segments disposed in parallel each other with a predetermined distance. The gate pad terminal GPT connects to the gate pad intermediate terminal IGT exposed through the second gate pad contact hole GH2. The data pad terminal connects to the data pad DP exposed through the data pad contact hole DPH.
After that, even though it is not shown in figures, the thin film transistor substrate having the pixel electrode PXL and the common electrode COM is sent to a chamber for forming an alignment layer. And then, depositing a liquid crystal layer and joining the color filter substrate, the liquid crystal display panel is formed.
Like this, according to the related arts, in order to manufacture the FFS type thin film transistor substrate for the flat panel display having the oxide semiconductor material, at least nine mask processes are required. As the number of the mask processes is increased, the manufacturing process is complicated, the possibility of problem may be increased and the cost would be expensive. Therefore, it is very important to reduce or simplify the manufacturing process for the thin film transistor substrate which has most elements of the liquid crystal display.